Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)

A new technical paper, “Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL,” was published by researchers at Barcelona Supercomputing Center. Abstract “The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe’s capacity in the design and manufac